1. Technical Field
The inventive concept relates to a resistance memory device, and more particularly, to a phase-change memory device and a method of fabricating the same.
2. Related Art
A phase-change memory devices that is one of nonvolatile memory devices includes a phase-change material of which resistance is changed depending on temperature. As the phase-change material, there is typically a chalcogenide material including germanium (Ge), antimony (Sb), and/or tellurium (Te). The phase-change material is changed into an amorphous state or a crystalline state depending on temperature to define a reset state (or logic “1”) or a set state (or logic “0”).
A memory cell of the phase-change material layer may include a variable resistor configured of a phase-change material and a switching device configured to selectively drive the variable resistor that are connected between a word line and a bit line.
As the switching device of the phase-change memory device, a diode occupying a small area has been mainly used.
An early diode is formed by doping impurities into a polysilicon layer patterned using a general photolithography process.
However, it is a trend to require a diode and a heating electrode having a critical dimension (CD) equal to or less than resolution of exposure equipment. In order to meet these demands, the diode and the heating electrode having the CD equal to or less than the resolution of the equipment are formed by forming a hard mask layer for confining a diode and a heating electrode region using double spacer patterning technology (SPT) and patterning a lower layer using the hard mask layer.
However, when a heating electrode layer and a diode layer are etched using the hard mask, since a thickness of a film to be etched is very large, leaning occurs and thus the phase-change memory becomes in an unstable state.
In particular, as illustrated in FIG. 1, a phase-change material layer 10 has a positive slope due to the leaning and thus a location in which phase-change is generated in the phase-change material layer 10 is biased downward. In FIG. 1, “A” indicates a location in which phase-change is normally generated when the leaning is not generated, and “B” indicates a location in which the phase-change is generated when the leaning is generated. When the phase-change generation location is changed, heat loss is generated to a side of a barrier layer 15 below the phase-change material layer 10.
When the phase-change memory device is fabricated, a double SPT process may be performed, and the heating electrode layer and the diode layer may be simultaneously etched using a mask material obtained the double SPT process. Thus, etching failure may occur and long fabrication processing time may be required.